1. Technical Field
The descriptions herein relate to a delay locked loop (DLL) circuit and a method of controlling the same, and more particularly, to a DLL circuit that generates an internal clock signal whose phase is more advanced than a phase of an external clock signal and a method of controlling the same.
2. Related Art
In general, a conventional DLL circuit is used to generate an internal clock signal whose phase is more advanced than a phase of a reference clock signal obtained by converting an external clock signal by a predetermined time. The DLL circuit is also used to resolve the following problem: If an internal clock signal used in a semiconductor integrated circuit is delayed by a clock buffer and a transmission line, a phase difference is generated between the internal clock signal and an external clock signal, which results in lengthening an output data access time. As a result, in order to increase an effective data output period, the DLL circuit performs a control operation such that a phase of the internal clock signal is more advanced than a phase of the external clock signal by a predetermined time.
Referring to FIG. 1, a conventional DLL circuit includes a clock input buffer 10, a delay line 20, a fine delay unit 30, a clock driver 40, a delay compensating unit 50, a phase comparing unit 60, and a shift register 70.
The clock input buffer 10 buffers an external clock signal “clk_ext” and generates a reference clock signal “clk_ref”. The delay line 20 delays the reference clock signal “clk_ref” in response to a delay control code “dlycnt<1:n>” and generates a unit delay clock signal “clk_ud”. The fine delay unit 30 fine-delays the unit delay clock signal “clk_ud” and generates a delay clock signal “clk_dly”. The clock driver 40 drives the delay clock signal “clk_dly” and generates an output clock signal “clk_out”.
The delay compensating unit 50 delays the delay clock signal “clk_dly” by a predetermined time and generates a feedback clock signal “clk_fb”. The phase comparing unit 60 compares phases of the reference clock signal “clk_ref” and the feedback clock signal “clk_fb” and generates a phase comparison signal “phcmp”. The shift register 70 generates a plurality of bits of digital code signals in response to the phase comparison signal “phcmp”, and outputs the plurality of bits of digital code signals as the delay control code “dlycnt<1:n>”.
The delay applied to the reference clock signal “clk_ref” by the delay line 20 varies according to a logical value of the delay control code “dlycnt<1:n>”. That is, the reference clock signal “clk_ref” is delayed by a predetermined time by the delay line 20, and the predetermined delay time of the reference clock signal “clk_ref” varies according to the logical value of the delay control code “dlycnt<1:n>”. The logical value of the delay control code “dlycnt<1:n>” is changed by one bit for each loop period of the DLL circuit. Accordingly, at the time of the initial operation of the DLL circuit, if the phase difference between the reference clock signal “clk_ref” and the feedback clock signal “clk_fb” is large, then the locking time increases, i.e., time that is needed until the delay line 20 has a locked delay value increases.
In recent years, as the operational speed of conventional semiconductor integrated circuit has increased, it has been required for the DLL circuit to have a fast locking time. However, in a conventional DLL circuit, which uses a shift register and a delay line to perform a delay locked operation, there is a technical limitation on how fast the locking time can become. In order to support the high-speed operation of today's semiconductor integrated circuits, a DLL circuit that can drastically decrease the locking time is beneficial.